[PATCH v1 2/2] riscv: extend support to 32 bit hosts

Karol Gugala kgugala at antmicro.com
Sat Feb 6 15:18:25 UTC 2021


64 and 32 bit targets share most of the code.
The only difference is supported ioctls and syscalls.

Signed-off-by: Karol Gugala <kgugala at antmicro.com>
---
 configure.ac              | 4 ++++
 linux/riscv/ioctls_inc0.h | 6 ++++++
 linux/riscv/syscallent.h  | 8 +++++++-
 riscv.c                   | 4 ++--
 4 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/configure.ac b/configure.ac
index 74b64089..a9a37fd8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -152,6 +152,10 @@ riscv64*)
 	arch=riscv
 	AC_DEFINE([RISCV64], 1, [Define for the RISC-V 64-bit architecture])
 	;;
+riscv32*)
+	arch=riscv
+	AC_DEFINE([RISCV32], 1, [Define for the RISC-V 32-bit architecture])
+	;;
 s390)
 	arch=s390
 	AC_DEFINE([S390], 1, [Define for the S390 architecture.])
diff --git a/linux/riscv/ioctls_inc0.h b/linux/riscv/ioctls_inc0.h
index f9939faa..195c8cf9 100644
--- a/linux/riscv/ioctls_inc0.h
+++ b/linux/riscv/ioctls_inc0.h
@@ -1 +1,7 @@
+#ifdef RISCV64
 #include "64/ioctls_inc.h"
+#elif RISCV32
+#include "32/ioctls_inc.h"
+#else
+#error "Unsupported RISC-V bit width"
+#endif
diff --git a/linux/riscv/syscallent.h b/linux/riscv/syscallent.h
index 60c6ce58..ee91ae4c 100644
--- a/linux/riscv/syscallent.h
+++ b/linux/riscv/syscallent.h
@@ -1,11 +1,17 @@
 /*
- * Copyright (c) 2016-2019 The strace developers.
+ * Copyright (c) 2016-2021 The strace developers.
  * All rights reserved.
  *
  * SPDX-License-Identifier: LGPL-2.1-or-later
  */
 
+#ifdef RISCV64
 #include "64/syscallent.h"
+#elif RISCV32
+#include "32/syscallent.h"
+#else
+#error "Unsupported RISC-V bit width"
+#endif
 
 /* #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) */
 [259] = { 3,	TM,		SEN(riscv_flush_icache),	"riscv_flush_icache"	},
diff --git a/riscv.c b/riscv.c
index 825eb293..b2dde0d8 100644
--- a/riscv.c
+++ b/riscv.c
@@ -1,7 +1,7 @@
 /*
  * RISC-V-specific syscall decoders.
  *
- * Copyright (c) 2018-2019 The strace developers.
+ * Copyright (c) 2018-2021 The strace developers.
  * All rights reserved.
  *
  * SPDX-License-Identifier: LGPL-2.1-or-later
@@ -9,7 +9,7 @@
 
 #include "defs.h"
 
-#ifdef RISCV64
+#if defined(RISCV64) || defined(RISCV32)
 
 # include "xlat/riscv_flush_icache_flags.h"
 
-- 
2.29.2



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